Location: Belfast, County Antrim, Northern Ireland, UKWe are recruiting an experienced Senior IP Design Engineer to join a leading technology programme delivering next-generation FPGA and Adaptive SoC solutions. This is a remote UK contract offering the opportunity to work on high-performance digital IP for cutting-edge systems.As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL, developing synthesis-ready IP targeting FPGA / Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place-and-route (P&R), constraints and optimisation. The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows.Key ResponsibilitiesDesign high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoCDeliver synthesis-ready RTL meeting timing, P&R and integration requirementsImplement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocksDrive timing closure using Vivado toolchainsDevelop automation using Python/Tcl scriptingCollaborate with hardware, SoC, firmware and integration teamsEssential SkillsStrong SystemVerilog RTL design experienceFPGA/Adaptive SoC design flow: synthesis, P&R, timing closureHigh-speed digital interfaces: 100GbE / PCIe Gen5 / AXIVivado / Vitis toolchain expertisePython/Tcl, Git, CI/CD experienceDetailsContract: 6 months + extensionLocation: Remote (UK)Start: ASAPRate: Market rateIf you are a Senior IP Design Engineer with strong FPGA RTL, high-speed interface IP and Xilinx toolchain experience, please apply with your CV for immediate considerationTPBN1_UKTJ