Principal Design Team Lead – AccelerComm Ltd Description As the Principal Design Team Leader at AccelerComm, you will be working on 5G base stations on board satellites. This revolutionary technology is at the leading edge of satellite communications and will underpin the next generation of mobile standards, giving complete global coverage. AccelerComm develops base‑band signal processing technology, using hardware acceleration to deliver world‑leading power efficiency. The Principal Design Team Lead will shape the technical roadmap to extend power efficiency for the latest generation of space‑qualified devices and deliver this technology to our customers. Key Responsibilities

Provide strategic vision to inform technical decision‑making and planning at a company level. Take responsibility for the successful and timely delivery of projects by providing technical leadership. Provide managerial leadership to build knowledge and support the team’s development. Work closely with the executive team to translate product requirements into hardware deliverables. Support discussions with customers during presales and product development. Implement designs targeting both FPGA and ASIC using industry‑standard techniques, including the creation of UVM‑based testbenches. Lead AccelerComm’s engineering methodology, processes, and design techniques. Nurture the professional growth of team members through regular mentoring, coaching, and feedback.

Essential Skills And Experience

Track record of building and leading high‑performing collaborative teams. Expert knowledge of RTL design (Verilog, SystemVerilog) for complex ASIC/FPGA products. Strong skillset in delivering digital designs for ASIC and FPGA. Optimization of timing and hardware resources for high‑throughput data or signal‑processing applications, including experience in power‑management techniques, synthesis and timing analysis. Expert user of EDA tools for simulation and synthesis. Knowledge and appreciation of project‑management methodologies across the design lifecycle, including Agile and Waterfall, requirements capture and traceability.

Desirable

Knowledge of communications signal‑processing algorithms (e.g., error correction, equalisation, channel estimation, beamforming). Understanding of UVM verification techniques or practical experience using UVM for IP verification. Experience using C++/SystemC for design modelling and integration. Experience in Technology Readiness Models. Experience in system architecture of a multi‑disciplinary team project.

Additional Information

Department: Hardware Employment Type: Permanent Location: Southampton, UK Reporting To: Tim Rogers Seniority level: Director Employment type: Full‑time Job function: Design, Art/Creative, and Information Technology Industries: Design Services

#J-18808-Ljbffr