Role: Physical Design Engineer

Location: Hybrid - 2 days per week in Cambridge, UK

Duration: 5 months

IR35 Determination: Inside

Work within a project team of 6 people to develop the next generation of Mali GPU, handling multiple build blocks (~1.5 million instances each) within a hierarchical GPU through the full PnR flow from RTL to STA for multiple milestone release cycles. Provide regular detailed feedback to RTL designers, log details in Jira, and communicate directly via email/IM to push the PPA and achieve project goals within the project time scale.

Your blocks will have hierarchical dependencies, requiring close collaboration with team members and sharing information across project teams to avoid inefficiencies.

You will be responsible for all stages from RTL to STA including logical equivalence checking (LEC) and conformal low power (CLP) checking. This will also include constraint and UPF development and debug.

Overview:

In this role your directive will be to influence RTL development for best-in-class PPA whilst innovating, crafting, and deploying the latest implementation techniques on live projects pushing the boundaries of power, area and frequency.

Responsibilities

• Physical implementation of Arm graphics processors using the entire implementation flow from RTL through place and route to STA.
• Supplying RTL feedback to designers via Jira to improve PPA and remove implementation bottlenecks.
• Collaborating with EDA vendors to solve tool issues and advance PPA.
• Planning and scheduling of own work inline with the project goals and needs.

Experience

• Cadence: Genus, Innovus, Tempus, QRC & Conformal
• PnR Flow: Synthesis, LEC, CLP, Floorplan, Placement, CTS, PostCTS, Routing, STA
• Synopsys: Fusion compiler, Formality
• Synthesis, LEC
• Low power design techniques (power gating, DVFS etc.)
• Understanding in building flows and methodology using scripting languages such as TCL, Python, Perl to support project development.

Experience/Skills

• Attention to details and tenacity to chase down problems
• Interpersonal and teamwork skills
• Relevant industry experience particularly around N3P/N2P technology nodes.