Location: UKJob Title: Senior IP Design Engineer Location: Cambridge OR London OR Milton Keynes (Hybrid- 1-2 Days)Duration: Fixed term contractJob Overview:Scope of WorkThe selected engineer will work closely with internal architecture, RTL, verification, and integration teams to design, implement, and optimize IP targeting AMD Adaptive SoCs. Responsibilities include:Developing RTL in SystemVerilog for high-performance FPGA / Adaptive SoC designsImplementing and optimizing high-speed connectivity protocolsCollaborating with cross-functional teams on integration, timing closure, and validationDriving improvements across synthesis, place and route, and timing flowsSupporting CI/CD development workflows using Git and scripting automationRequired Skills & ExperienceThe proposed candidate must meet the following qualifications:A. RTL Design & CodingDeep hands-on experience with SystemVerilog HDL for RTL designProven ability to develop IP targeting FPGA / Adaptive SoC platformsB. High-Speed ProtocolsStrong experience with:100Gb EthernetPCIe Gen5AMBA / AXI interface protocolsC. Adaptive SoC / FPGA ExpertiseIn-depth understanding of FPGA / Adaptive SoC development flows, including:SynthesisPlace and routeTiming analysis and closureD. AMD Toolchain ExperienceHands-on experience with AMD Vivado / Vitis tools and associated flowsE. Scripting & AutomationProficiency in scripting: Python, TclAble to automate design, build, and verification workflowsComfortable with Git for CI/CD integrationDeliverablesRTL IP blocks developed in SystemVerilog according to project specificationTiming-closed design implementations for target Adaptive SoCsDocumentation for IP integration and usageScripts and automation to support CI/CD workflowsWeekly status updates and participation in technical reviewsTPBN1_UKTJ