Senior IP Design Engineer
New Yesterday
Location: Cambridge OR London OR Milton Keynes (Hybrid- 1-2 Days)Duration: Fixed term contractJob Overview: Scope of Work
The selected engineer will work closely with internal architecture, RTL, verification, and integration teams to design, implement, and optimize IP targeting AMD Adaptive SoCs. Responsibilities include:
Developing RTL in SystemVerilog for high-performance FPGA / Adaptive SoC designs
Implementing and optimizing high-speed connectivity protocols
Collaborating with cross-functional teams on integration, timing closure, and validation
Driving improvements across synthesis, place and route, and timing flows
Supporting CI/CD development workflows using Git and scripting automation
Required Skills & Experience The proposed candidate must meet the following qualifications:
A. RTL Design & Coding Deep hands-on experience with SystemVerilog HDL for RTL design
Proven ability to develop IP targeting FPGA / Adaptive SoC platforms
B. High-Speed Protocols Strong experience with:
100Gb Ethernet
PCIe Gen5
AMBA / AXI interface protocols
C. Adaptive SoC / FPGA Expertise In-depth understanding of FPGA / Adaptive SoC development flows, in...
- Location:
- Stoke-On-Trent
- Job Type:
- FullTime
- Category:
- Engineering